ssp-21116 description the ssp-21116 series of 270 volt, dc, solid-state power controllers (sspcs) replace electromagnetic circuit breakers and solid-state relays rated from 2 through 15 amperes. these sspcs offer status outputs and permit external input logic control so that they may be remote- ly located near to the load. there are four models in the series, differing only in rated current, so that fault and i 2 t trip characteristics can be selected to protect wiring and loads. using power mosfet switches, these power controllers offer low "on" resistance, low voltage drop, high "off" impedance, and low power dissipation. built with power mosfets and custom monolithics and using thick film hybrid technology, they offer small size, low power and high reliability. built-in-test (bit) has been provided to monitor, in real time, the status of the internal circuitry as well as circuitry exter- nal to the sspc. this bit monitors mosfet failure and control circuit fail- ure. the ssp-21116 series will operate over the full mil temperature range from -55c to +125c with no thermal derating (see ordering information). applications designed to replace circuit breakers in land, air and space vehicles, these solid- state power controllers provide status outputs for light and heavy overloads as well as minimum load current. features ? true i 2 t protection ? isolated control circuitry ? status outputs ? instant trip protection ? leakage clamp ? low power dissipation ? solid-state reliability vcc1 vcc2 mosfet driver, short circuit control, vee1 vbias supply input status circuit, and isolated control circuit status1 status2 vbias supply common latches internal power supplies r sense power in pins 6,7 pins 6,7 power out pins 9,10 pins 9,10 slew control pin 8 pin 8 high side switch config. low side switch config. +28 vdc +28 vdc load load or system gnd power in power out slew control control cmd ? 1990, 1999 data device corporation figure 1. ssp-21116 block diagram 270 vdc solid-state power controllers
2 +150 c junction temperature -1000 to +1000 vdc pin-to-case -0.5 to +7.0 vdc v bias voltage (see note 4) vdc vdc vdc value unit parameter table 1. absolute maximum ratings parameter unit value vdc vdc vdc +60.0 to +300.0 0 to v bias -300 to +300 v bias voltage (see note 4) vdc +4.5 to +5.5 table 2. recommended operating conditions power input to power ground control input to signal ground power ground to signal ground 450 continuous 500 volts, 50ms transient -0.5 to +7.0 -1000 to +1000 power input to power ground control input to signal ground power ground to signal ground table 3. ssp-21116 specifications (see notes 1 and 2) parameter conditions unit value control circuit logic type ttl/cmos compatible v bias supply current v cc = 4.5 to 5.5vdc ma 25typ control turn-on voltage v 2.0 to 5.5 control turn-off voltage v -0.5 to 0.8 control input current control voltage = 5.0v m a 50max control input current control voltage = 2.4v m a 50max control input current control voltage = 0.8v m a -50min status output voltage v cc = 4.5v, i ol = 2.5ma v 0.4max status output voltage v cc = 4.5v, i oh = -1.0ma v 2.4min status truth table see table 5 power circuit power out voltage with switch off power in = 60 - 300v no load v 30max max. continuous current see table 4 'on' resistance see table 4 power dissipation see table 4 power out leakage current to power gr ound power in = 60 - 300v (see note 2 ) ma/a 0.1max max load capacitance for start-up power in = 60 - 300v (see note 2 ) m f/a 4typ signal to neutral ground isolation at 100vdc pf 1000typ output capacitance see note 2 pf/a 300typ trip reset time ms 30min rupture capacity unlimited a unlimited output-to input parasitic diode, continuous current per amp of rated current power out voltage > power in voltage a 1.0typ output-to input parasitic diode, pulsed current per amp of rated current power out voltage > power in voltage pulse width 100 m s a 4.0typ table 3. ssp-21116 specifications (see notes 1 and 2) parameter power circuit (continued) conditions unit value output-to input parasitic diode, forward voltage at continuous current power out voltage > power in voltage v 1.8max isolation resistance, any pin to case pin-to-case voltage = 100vdc m w 50min isolation resistance power ground to signal ground power ground to signal ground voltage = 500vdc m w 50min voltage drop across pins 6&7, 9&10 vdc see note 3 trip characteristics see figure 2 response time see figure 3 temperature range operating (baseplate) storage c c -55 to +85 -55 to +125 thermal resistance case to sink ( q cs ) case to ambient ( q ca ) c/w c/w 0.4 6 temperature rise, junction-to-case rated load c 10 physical characteristics size weight see figure 4 g 115 note: power ground = neutral; bias supply common = signal ground notes: 1. -55c case temperature 125c. 2. 'a' is amps of rated sspc current. 3. for 2a, 5a, and 10a units the value is 1v max; for 115a unit the value is 1.5v max. 4. an external 0.1f ceramic capacitor from v bias to the +5v return ground is recommended. table 4. part number i-max*(amps) 'on' resistance (ohms)** power dissipation (watts)** ssp21116-002 2 0.460 2.0 ssp21116-005 5 0.160 4.2 ssp21116-015 ssp21116-010 15 10 0.085 0.085 19.3 8.7 * i-max is the maximum continuous current. ** specified for -55c to +105c;increases 0.6%/c between +105c and +125c. note: other amp ratings are available, consult factory. functional description the ssp-21116 series of solid-state power controllers incorpo- rate the wire protection feature of electromechanical circuit breakers and the reliability of solid-state relays. in addition to the solid-state relay's input logic compatibility, the ssp-21116 series provide logic compatible status outputs. a ttl/cmos compatible input provides external control of the power switch's "on/off" state. a logic high on this control input turns the power to the load "on". a logic low will turn the power switch off, which removes power from the load. +300 c lead temperature (soldering) power in to power ground v 0 to 300
in the event of an overload, the ssp-21116 series will trip, just like a circuit breaker, and automatically remove power from the load. in order to turn back on, the control input must be brought to a logic low, and then returned to a logic high state. as in a circuit breaker, the sspc's time to trip depends on the current level. slight overloads will cause longer trip times. heavy overloads will cause shorter trip times. the fault ("instant trip") and i 2 t trip curve, figure 2, shows the trip time as a function of current for a single trip or repetitive trips with at least 10 sec- onds between trip and turn on. attempts to repeatedly turn on into an overload will result in the thermal memory shortening each trip time. this "memory" protects the wire, load and solid- state power controller. the status lines are ttl/cmos compatible outputs which reflect the state of the sspc, the load and the built in test (bit) circuits. the status permits an external subsystem to monitor and ulti- mately control the sspc. table 5 defines the status lines' states which indicate the various states of the sspc. further explanation of the status lines appears in the applications infor- mation section. the ssp-21116 series sspc's are characterized by their current rating and maximum "on" resistance listed in table 4. these parameters are established by the number of power fet's placed in parallel within the sspc. the trip function is implemented by two separate circuits, a true i 2 t trip comparator and a short circuit fault comparator. they are independent of each other but work together to protect the sys- tem. if the load current is less than 110% of rated current, the sspc will never trip. if the load current is greater than 145%, the sspc will always trip. for load currents less than 800%, the trip time can be found from figure 2 by drawing a horizontal line on figure 2 at the cur- rent level of interest. the sspc will always trip at a time between the two curves. this is true i 2 t tripping. when the sspc trips in accordance with the i 2 t characteristics, the fall time is 200 s, maximum. for load currents greater than 1200%, the sspc will turn off in less than 25 m s. between 800% and 1200%, the sspc will turn off in a time less than the "max. trip limit" shown in figure 2 and may turn off in less than 25 m s. when the sspc turns off under these fault conditions, the fall time is less than 25 m s. while the sspc will always turn off in less than 25 s when the load current is greater than 1200%, the actual current may 'spike' to a value higher than 1200% due to circuit delays. the mosfet's inherently self limit the maximum current, depending on the number of mosfet's and their rating. during turn on and turn off the rise and fall time of the output volt- age is controlled to be less than 200 m s. this value is a com- promise between faster response time with a greater amount of rfi and emi generated, and slower response time with less rfi and emi but greater power dissipated in the sspc during transi- tions. since the power mosfet switches are not saturated dur- ing transitions the switching power dissipation is much greater than the static dissipation, and longer transitions result in a larg- er temperature rise. if the sspc is rapidly turned on and off, the high average dissipation could result in a significant temperature rise in the sspc. for this reason do not turn the sspc off and on more rapidly than 30 msec. this will limit the maximum tem- perature of the switches to a safe level. the ssp-21116 has been designed to derive its internal power requirements from the bias supply input (+5 vdc). 3 10,000 1,200 1,000 800 600 400 200 0 10 1.0 0.1 0.01 0.001 m s 25 145% 110% load current % i - max time - seconds always trip never trip max. trip limit instant trip m i n . t r i p l i m i t figure 2. trip characteristics
applications information selection the selection of a proper sized sspc is essential for protection of the wire and load. this selection should be based on the steady state and transient overload currents. the shape of the trip curve (i 2 t) is selected as optimum to pro- tect the system wiring. the power dissipated in the wire is the wire resistance times the load current squared, and the temper- ature of the wire is determined by the length of time that this power is being dissipated. this makes the wire temperature pro- portional to the current squared times the on time. since the trip curve follows this same characteristic the sspc can accurately predict the wire temperature rise as a result of overloads and remove load current before the wiring is damaged from overtem- perature. of course, the wire i 2 t product should be greater than the sspc i 2 t product for the sspc to protect the wire. precautions when a short circuit causes turn off of the sspc, precautions have to be taken to limit the transient voltages generated by the wire inductance. the magnitude of this voltage is l*di/dt where "l" is the wire inductance in henries and "di/dt" is the rate of change of output current. if the sspc turns off in 10 msec from a 150 amp overload (1000% for 15 amp unit) with a wire induc- tance of only 33 mh it would generate a spike of 500 volts. this exceeds the voltage rating of the mosfet's. in order to provide protection from these transients, transient voltage suppressors should be used between the sspc neutral and the power in and between the sspc neutral and power out terminals. the rating of the transient voltage suppressors should be selected so that at the maximum expected short circuit current, the transient volt- age suppressor voltage drop would not exceed the sspc volt- age rating, and the power to be dissipated can be safely absorbed without transient suppressor failure. while circuit inductance can cause high voltage transients dur- ing turn off, lack of circuit inductance can cause current tran- sients prior to turn off. if the output of the sspc is shorted and there is no circuit inductance, the current from the source can rise instantaneously to a high value. the sspc will limit the cur- rent to about 30 times its rating (3,000%). circuit inductance will limit the rate of rise of this current. the sspc can take 25 s to turn off. the current will always overshoot the 1200% maximum level of the sspc due to this 25 s delay. if the current rises slowly due to circuit inductance, the overshoot will be negligible; if the current rises quickly, the overshoot will be more significant. in any case, the current spike will be less than 25 s. 4 control input load current trip point status 2 status 1 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 solid-state power controller timing at 28 vdc. time description maximum unit notes t1-t2 turn-on delay 350 m s t2-t3 current rise time 200 m s t1-t4 status 1 & status 2 turn-on delay 7.5 ms t4-t5 status 1 & status 2 rise and fall time 350 ns t6-t7 turn-off delay 350 m s t7-t8 current fall time 200 m s t6-t9 status 1 & status 2 turn-off delay 5.0 ms t10-t11 trip time after turn-on see fig. 2 s t11-t12 current fall time after trip 200 m s load current < 800% t11-t12 current fall time after trip 25 m s load current > 1200% t11-t13 trip turn-off status 1 delay 5.0 ms figure 3. solid-state power controller timing
cycling the input control to a logic low and then back to a logic high. if the excessive load has not been removed, the sspc will trip again. 8) no load current. status 1 indicates the load is not draw- ing current; status 2 indicates the power mosfet switch is on. loads the ssp-21116 series can be used with any type of load: any combination of inductive, resistive, and capacitive. in addition, they can be used with dc motors and lamps. inductive loads require protecting the sspc against voltage tran- sients. see the section on precautions above. capacitive loads require comparing the load inrush current to the trip curve of figure 2. the inrush current must be below the minimum trip curve to avoid tripping on the inrush current. capacitive loads can present a discharge problem. the sspc's use power mosfet's as the switching element. the mosfet's contain a parasitic diode which will be forward biased if the sspc power output terminal is more positive than the power input terminal. if the 270 vdc source is turned off while a charge is held on the capacitive load, this diode will turn on and dis- charge the load through the generator. the sspc can carry a reverse current equal to its forward current rating; however, the dissipation with reverse current is up to four times the forward current dissipation for the same current. the user must ensure that the maximum case temperature is not exceeded. in most real applications, there will always be significant circuit inductance. the problem to guard against is voltage transients, not current transients. when testing individual sspc's, be careful to simulate actual system conditions. power on reset when the 5 v bias power is first applied, the sspc will be off regardless of the control cmd input. if the control cmd input is a logic low, the sspc is turned on by bringing the con- trol cmd to a logic high. if the control cmd input is at a logic high when power is applied, the sspc may be turned on by cycling the control cmd input to a logic low and then to a logic high. the system controller can be programmed to do this cycling of the control cmd input. subsequent loss of the bias supply power causes the sspc to turn off. re-application of the bias supply power again causes a power on reset (refer to optional power on reset.) loss of power to the power in ter- minals does not turn off the sspc and re application of this power does not cause a power on reset. status codes this section contains a fuller explanation of the conditions and meaning of the status codes shown in table 5. each paragraph number corresponds to the state in table 5. the first four conditions show the control input has commanded the sspc to be off. 1) the sspc has failed or shorted to ground. status 1 indicates the load is drawing current but the sspc should be off. 2) the sspc has failed. status 1 indicates the load is drawing current; status 2 indicates the power mosfet switch is on; the sspc should be off. 3) normal off condition. status 1 indicates the load is not drawing current; status 2 indicates the power mosfet switch is off. 4) the sspc has failed or status 2 has shorted to the bias supply. status 1 indicates the load is not drawing current; status 2 indicates the power mosfet is on ; the sspc should be off. the next four conditions show the control input has commanded the sspc to be on. 5)the sspc has failed or there is a short to ground on the status 2 output. status 1 indicates the load is drawing current but status 2 indicates the power mosfet switch is off. 6)normal on condition. status 1 indicates the load is drawing current and status 2 indicates the power mos- fet switch is on. 7)tripped condition. status 1 indicates the load is not drawing current and status 2 indicates the power mos- fet switch if off. the sspc can be turned back on by 5 table 5 state output status 1 (see note 2) output status 2 (see note 3) power controller and load status 1 l l l 2 l l h 3 l h l load off; showing normal off condition. 4 l h h sspc failure or status 2 shorted to bias supply. 5 h l l sspc failure or short to ground on status 2 line. 6 h l h load is 'on', showing nor- mal on condition. 7 h h l load is 'off, showing trip (see note 1). 8 h h h normal power out with load <5% of rated sspc current. notes: 1) any trip condition per figure 2. 2) status 1 indicates a logic low when the load is > 15% of the rated sspc current. 3) status 2 indicates a logic high when the power mosfet switch is on. input control cmd sspc failure or short to ground. load on; showing sspc failure.
incandescent lamps must be treated like capacitive loads for inrush current. since they do not store charge, they do not pre- sent a discharge problem. dc motors also must be treated like capacitive loads for inrush current. if they continue rotating when power is removed, reverse current is a possibility due to back emf. voltage transients must also be considered when using dc motors as loads on sspc's. heatsinking the ssp-21116 series are designed so that the junction tem- perature can never exceed its maximum rating if the case tem- perature is held to 125c or less. heatsinking is recommended to keep the case temperature to 125c when operating at high ambient temperatures. the sspc's may be operated at room temperature without a heat sink. the maximum ambient tem- perature, t a , for operation without a heat sink is 125 - p d x q ca (where pd is the power dissipation from table 4 and q ca is the thermal resistance from case-to-ambient from table 3). the same expression is used for finding the maximum ambient temperature with a heat sink except q ca is now the sum of the thermal resistance from case-to-sink and from sink-to-ambient. no offset voltage the power mosfet used in the ddc sspc's have no inherent voltage offset. the voltage drop across the power mosfet is sole- ly dependent on the current flowing through the device and its "on" resistance. bipolar transistors, on the other hand, have an inherent dc offset voltage to which is added a voltage drop proportional to the devices' "on" resistance and the current flowing through it. it is this inherent offset voltage that is missing from the power mosfet. the power mosfet in many applications, leads to a lower voltage drop and power dissipation as an sspc switch. in addition the power mosfet's driver logic requirements are much simpler, especially when multiple mosfet's are used, as in the sspc product. no secondary breakdown, and paralleling sspc's a bipolar transistor has a set of current voltage limits that form an envelope that cannot be exceeded; this is known as the safe operating area of the device. if this envelope is exceeded local hot spots will occur. these hot spots conduct currents more readily then adjacent cool areas and tend to become hotter. this thermal runaway, or secondary breakdown , leads to the ultimate destruction of the device. the power mosfet's have the opposite characteristics from that of thermal runaway in bipolar devices. a local hot spot will steer current away from itself as its resistance in this area goes up. this results in even current sharing throughout the entire device, thereby eliminating hot spots. the inherent advantage of not having secondary breakdown is that the entire mosfet has to exceed its temperature limitations before damage results. this characteristic makes the power mosfet more rugged when used for power switching then bipolar devices. due to the current sharing aspects of the power mosfet, they can be placed in parallel and share the load equally. ddc has a stan- dard 28 vdc 80 amp power module which uses this technique. isolation of control and status the sspc was designed with isolation between the load power and the five volt control logic input and the status outputs. this is necessary to prevent noise caused by transients or power spikes on the power line from adversely affecting the operation of the sspc. therefore the case, power in and the control circuit are all electrically isolated. figure 1 shows this isolation as the "isolated control circuit"; also notice the separation of the power (neutral) ground and signal (bias supply common) ground. the electrical isolation is supported by an internal power oscilla- tor that electrically isolates separate internal power supplies that will power the internal analog and digital monolithics. this isola- tion prevents load or logic ground loops from affecting the prop- er operation of the sspc. the isolation also insures that a fault of the switch (mosfet) could never propagate back into the sspc logic or cause damage to the logic side. options the following characteristics can be factory modified on special orders: ? i 2 t trip curve: k-factor adjustments ? output rise and fall times: turn-off and turn-on time can be factory modified (e.g., capacitive loads) ? current range ? power-on reset: other (v bias) options are available ? leakage clamp: can be deleted ? input control: ttl or cmos or both with hysteresis (schmitt trigger characteristics) ? custom packaging: dip, flat pack, or smaller 2-5 amp package ? optional status truth table (see table 6) 6 table 6. optional status truth table control low sspc failure, or status 1 and sta- tus 2 shorted to ground, or no bias system status sspc failure or status 1 shorted to ground sspc failure or status 2 shorted to ground load off, normal condition low low low status 1 low low low status 2 sspc failure or status 2 shorted to ground load on, normal condition load is off, tripped low low status 1 indicates a logic low if > 15% of the rated current flowing. status 2 indicates a logic low if the sspc is tripped due to overcurrent. low low low high high high high high high high high high high high high load is on, load < 0.5% rated current
7 figure 5. mechanical outline for 7-15 amp dip packaging figure 4. mechanical outline for 2-5 amp packaging 0.600 (15.24) 1.340 (34.04) 1.025 (26.04) 0.800 (20.24) 0.270 (6.86) 0.112 (2.85) 0.200 (5.08) 0.400 (10.16) 1.550 (39.37) 0.040 0.002 dia pin (5 req'd) (1.02 0.05) 2.525 (64.14) 2.740 (69.60) 0.595 (15.11) 5 4 3 2 1 6 7 8 9 10 contrasting colored bead to denote pin 1 pin numbers for ref only 0.062 0.002 dia pin (5 req.d) (1.58 0.05) 0.117 + 0.004 - 0.003 dia (4 holes) (2.97 + 0.10 - 0.08) 2.280 (57.91) 0.470 (11.94) front view bottom view side view 0.065 (1.65) 0.240 0.010 (typ) (6.10 0.25) 0.325 max (8.26) dimensions are in inches (mm) 0.105 (2.67) 0.105 (2.67) 1.54 (39.12) 2.000 (max) (50.8) 3.000 (max) (76.20) 0.23 (5.84) 89 16 1 2.54 (64.52) bottom view side view dimensions are in inches (mm) 0.325 max (8.26) 0.065 typ (1.65) 0.240 0.010 typ (6.10 0.25) 0.030 (0.76) 0.26 (6.60) 0.125 dia (4 holes) (3.18) 1.48 (37.59) 0.45 (11.43) pin 1 denoted by contrasting colored bead 7 eq. sp @ 0.300 = 2.100 (7.62 = 5.33) 0.300 typ (7.62) 0.040 0.002 16 reqd (1.02 0.05) note: see table 7 for pinouts. note: see table 8 for pinouts.
ordering information ssp-21116-xxx -x reliability grade: b = hybrids screened to mil-prf-38534 but without qci testing blank = standard ddc procedures xx - current in amps (1) temperature range (2) : 0 = -55c to +125c 1. see table 4 for available current ranges. consult factory for other current ranges. 2. consult factory for other temperature ranges are available. 8 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. g-04/98-1m table 7. pinouts for figure 4. pin function pin function 5 4 3 2 1 control command status 1 status 2 bias supply common bias supply input 6 7 8 9 10 power in power in neutral power out power out table 8. pinouts for figure 5. pin function pin function 1 2 3 4 5 6 7 8 power out power out power out neutral nc nc nc nc 16 15 14 13 12 11 10 9 power in power in power in bias supply common bias supply input status 1 status 2 control command printed in the u.s.a. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7381 headquarters - tel: (631) 567-5600 ext. 7381, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com ilc data device corporation registered to iso 9001 file no. a5976
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